External crystal oscillators and internal precision oscillators (IPOs) are used to provide clock signals for many electronic circuits and applications. Although an external crystal oscillator provides an accurate oscillation frequency, a crystal oscillator is usually more expensive and less reliable. Therefore, an internal precision oscillator (IPO) is sometimes preferred over an external crystal oscillator. However, IPOs are implemented on semiconductor chips (known as Integrated Circuits) and could generate inaccurate oscillation frequencies due to production-related parameter fluctuations (i.e., process, voltage and temperature variations). For systems or inter-system communications that require a high precision target frequency, an IPO generally needs to be tested such that it generates an oscillation frequency that is substantially equal to the target frequency. Commonly, the oscillation frequency of an IPO is dependant upon a trim value representing either resistance or capacitance within the IPO. During the testing process (also known as trimming), the oscillation frequency is calibrated with respect to the target frequency by adjusting the trim value.
FIG. 1 (prior art) is a diagram of a microcontroller integrated circuit 1 and a production tester 2 (Teradyne J750 as illustrated). Microcontroller integrated circuit 1 includes a RC IPO 3, an on-chip debugger 4, a trim register 5, and a parallel data bus 6. Microcontroller integrated circuit 1 also includes terminal 7 and terminal 8. RC IPO 3 generates a clock signal that is output onto terminal 7. Tester 2 receives the clock signal from terminal 7. Tester 2 has a serial port 9. Serial port 9 of tester 2 is connected to terminal 8 of microcontroller integrated circuit 1 for serial communication.
FIG. 1 illustrates an example of a frequency trimming method for RC IPO 3 using production tester 2. In the example of FIG. 1, the frequency of the clock signal is dependant upon a 10-bit trim value that is stored in trim register 5. Tester 2 receives the clock signal and measures the frequency of the clock signal. Tester 2 then compares the measured frequency with a desirable target frequency (for instance, a frequency of 5.5296 MHz). If the measured frequency is different from 5.5296 MHz, then tester 2 sends out a new 10-bit trim value in serial digital format through serial port 9. On-chip debugger 4 receives the new trim value from terminal 8 in serial digital format and converts the new trim value to parallel format. On-chip debugger 4 then writes the new trim value into trim register 5 across parallel bus 6. RC IPO 3 then generates a clock signal with a different frequency that is closer to 5.5296 MHz due to the new trim value. Tester 2 measures the new frequency of the clock signal and repeats the same trimming process until the frequency of the clock signal is substantially equivalent to the target frequency of 5.5296 MHz.
This frequency trimming process for RC IPO 3 using tester 2 is performed for each chip individually and is time consuming. Extra cost and test latency is introduced for a number of reasons. First, a regular tester is usually designed for sending predefined inputs and checking predefined outputs. In order to measure frequency and make a decision in adjusting the trim value, tester 2 is more intelligent and therefore more expensive than a regular tester. Second, sending the new trim value in serial digital format through serial communication is slow. Third, tester 2 is occupied throughout the entire trimming process because it uses its serial port to communicate to microcontroller integrated circuit 1 through debug terminal 8. As a result, tester 2 may not be able to perform other tests during the frequency trimming process. The large amount of test time required to trim RC IPO 3 adds to the total cost of microcontroller integrated circuit 1. Therefore, it is desirable to reduce the amount of test time required to trim RC IPO 3.